The present invention relates to transistor fabrication, and more specifically, to transistors with uniaxial stress channels for high hole mobility.
Typically, in logic circuits, transistors are driven with high drive current (e.g., up to 100 mA). In order to attain the high drive current, the overall width of the logic devices is increased. However, silicon germanium (SiGe) channel p-type field effect transistors (pFET) show superior hole mobility especially in narrow width devices due to the uniaxial stress enhanced mobility. In contrast, as the width of the device increases, hole mobility is decreased. As such, if the device width is increased to achieve the overall drive current, the benefits of uniaxial stress in narrow width devices (i.e., high hole mobility) is not realized. To better utilize the uniaxial stress, and make the chip area efficient, approaches are desirable to manufacture array of narrow width pFET transistors, without sacrificing chip area.